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PART NUMBER:
± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
KXTF9-4100
Rev. 6
Jun-2011
CTRL_REG3
Read/write control register that provides more feature set control. Note that to properly change the
value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
R/W
SRST
Bit7
R/W
OTPA
Bit6
R/W
OTPB
Bit5
R/W
DCST
Bit4
R/W
OTDTA
Bit3
R/W
OTDTB
Bit2
R/W
OWUFA
Bit1
R/W
OWUFB
Bit0
Reset Value
01001101
I C Address: 0x1Dh
2
SRST initiates software reset, which performs the RAM reboot routine. This bit will remain 1
until the RAM reboot routine is finished.
SRST = 0 – no action
SRST = 1 – start RAM reboot routine
OTPA, OTPB sets the output data rate for the Tilt Position function per Table 14. The default
Tilt Position ODR is 12.5Hz.
OTPA
0
0
1
1
OTPB
0
1
0
1
Output Data Rate
1.6Hz
6.3Hz
12.5Hz
50Hz
Table 14. Tilt Position Function Output Data Rate
DCST initiates the digital communication self-test function.
DCST = 0 – no action
DCST = 1 – sets ST_RESP register to 0xAAh and when ST_RESP is read, sets this
bit to 0 and sets ST_RESP to 0x55h
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